H264 IP Camera System on Chip
NVS2200
H264 IP Camera System on Chip
DESCRIPTION
NVS2200 is a high performance cutting edge H.264 IP Camera SoC. It integrates high speed ARM9 processor core, high quality ISP, full duplex H.264 and M-JPEG encoder, 10/100Base-T Ethernet MAC controller and efficient peripherals. Video stream data from camera sensor will be processed by ISP module and then encoded simultaneously by H.264 and MJPEG engines. CPU can upload the compressed video stream through network line. The embedded ISP module features best image quality with CCD and CIS Sensor, 2D Noise Reduction Filter, AE/AWB, OSD and Motion Detection functions. NVS2200 has NTSC/PAL Encoder and builtin
10bit 2CH DAC for CVBS and IRIS. Built-in SD resolution H.264 encoder enables best quality performance and high compression ratio. In addition, it supports fully-hardwired crypto accelerator, SD card controller for emergency data store and full duplex I2S/SSP for audio interface. NVS2200 will be best fit for high performance and cost effective IP camera solutions
FEATURES
ARM9 RISC CPU embedded(210MHz, 16KB I/D-Cache)
High Quality ISP
- Supports Sony/Sharp CCD Sensor
- Supports OmniVision/Micron CIS
- NTSC/PAL, High/Normal, AE/AWB, 2D NRF
- Motion/defect detection, privacy zone, horizontal mirror
- On screen display(OSD)
Video capture
(CCIR656 input, maximum capture resolution up to
1280x1024)
H.264 Encoder
(MPEG-4 AVC/JVT/H.264(ISO/IEC 14496-10) standard)
- Encode D1 max 60fps
JPEG encoder(JPEG (ISO/IEC 10918-1) baseline standard)
- Encode D1 max 30fps
Crypto accelerator(DES, AES, SHA-1, MD5, Hash & HMAC)
DDR SDRAM memory controller
Static memory controller
10/100Base-T ethernet controller
3-port UART / SD card controller
16-pin GPIO / Timer / WDT / RTC / I2C / I2S
DAC for CVBS and IRIS
Package(289-TFBGA, 14mmx14mm, 0.8P)
BLOCK DIAGRAM
NVS2300
High Performance HD H264 IP Camera SoC
DESCRIPTION
NVS2300 is a high performance multi-codec(H.264/MPEG/MJPEG) IP camera SoC. It integrates 500MHz ARM9 processor with two 32KB I/D caches, high quality ISP, high performance H.264 encoder, MPEG4 encoder, MJPEG encoder, USB2.0OTG, PCI, 10/100Base-T Ethernet MAC controller and most efficient peripherals. Built-in DDR2 controller and NAND/NOR flash controller also play an important role for total BOM cost down. It has fully-hardwired crypto accelerator, SD card controller and high efficient audio DMA Interface module. NVS2300 will be one of the best cost-effective and performance-effective development platforms for various network security and IP camera applications.
FEATURES
ARM9 RISC CPU
- up to 533MHz , 32KB I/D-Cache, MMU
DDR2 controller
- 32bit DDR II-533 SDRAM interface
Video interface
- 2-Ch of BT.656 or 1-Ch of BT.1120 video input
- 1-Ch of BT.656 video output
- Maximum input capture resolution up to 1920×1080
- OSD(256 programmable 12×16 fonts)
High quality ISP
- Supports Sony/Sharp CCD sensor
- Supports Omnivision/Micron CIS
- NTSC/PAL, high/normal
- AE/AWB
- Defect detection, private zone
Video function module
- Motion detection up to 1920×1080 with 32×24 blocks
H.264 encoder
- MPEG4 AVC/JVT/H.264(ISO/IEC 14496-10) baseline profile
- up to 120 fps with D1 resolution, up to 15 fps with 1920×1080
- CBR and VBR rate control
- Resolution up to 1920×1080 stepped in 16
MPEG4 encoder
- MPEG4(ISO/IEC 14496-2) simple profile
- up to 30 fps with D1 resolution
M-JPEG encoder
- JPEG(ISO/IEC 10918-1) baseline standard
- up to 30 fps with D1 resolution
PCI bridge interface
- Compliant with PCI 3.0 specification
- 32bit/33MHz, 32bit/66MHz
USB2.0 OTG controller
- Supports UTMI+ level 3 compliant transceiver
- PHY included(LS, FS, HS, HUB function)
NAND/NOR flash controller
- NAND/NOR booting
- NAND flash capacity : max 2GB×4ea
Static memory controller(Host port interface)
10/100Base-T Ethernet MAC controller(RMII)
DMA controller
MMC/SD card controller(SDIO)
AES/DES/3DES/HASH
Audio DMA
TIMER, WDT, INTC, GPIO, I2C, I2S/SSP, UART, PMU
Linux 2.6.14, drivers, streaming player(VLC)
Power consumption : typical 870 mW(clock gating control)
1.2 V(core), 1.8 V(DDR2 I/O) and 3.3 V(I/O)
Package(432-TFBGA, 19 mm×19 mm, 0.8p)
BLOCK DIAGRAM
