H264 CODECS & DVR / NDVR SoC
CW5521
Programmable video codec-JPEG MPEG4 + H264
CW5521- Programmable video processor supporting MJPEG and MPEG4 encode and decode plus audio. Full source code for codecs available, other codecs in development. Low power solution with 656 or Bayer interface, USB and other hardware interfaces. This is a general purpose very low power DSP designed for video applications. MPEG4 at 30 fps and simultaneous MJPEG at 30 fps capability. H264 available soon.
CW5521- High performance low power programmable video codec.
NVS2200F
H264 JPEG MPEG4 Network DVR SoC
DESCRIPTION
NVS2200F provides a high performance surveillance solution to accelerate the image and video related applications such as the H.264, MPEG4, and JPEG to the end products. NVS2200F supports both MPEG4/JPEG and H.264 encoders/decoders. It provides the cost-effective and easy development system for the integration and verification of the video application at the early development stage. The NVS2200F system platform includes a wide range of basic components to reduce the overall system cost, including the H.264
codec, video capture, 656out_gen, LCD controller, DES/3DES controller, USB 2.0 OTG controller, USB 2.0 PHY, DMA controller, PCI Bridge, IDE controller, Ethernet MAC controller, and AMBA bus framework. NVS2200F will be best fit for high performance and cost effective IP camera solutions.
FEATURES
ARM9 RISC CPU embedded
(Up to 450MHz , 32KB I/D-Cache)
H.264 Codec
(MPEG4 AVC/JVT/H.264 (ISO/IEC 14496-10) baseline
profile)
- Max D1 60 fps@CPU 333MHz, H.264 166MHz
MPEG4 Codec(MPEG4 (ISO/IEC 14496-2) simple
profile)
- Max D1 30 fps@CPU 333MHz, MPEG4 166MHz
M-JPEG Codec(JPEG (ISO/IEC 10918-1) baseline
standard)
- Max D1 30 fps@CPU 333MHz, MJPEG 166MHz
Dual bit-stream throughput
: H.264(D1*30fps) + JPEG(D1*27fps)
Video capture(2 CCIR656 inputs, maximum capture
resolution up to 1280 x 1024)
ATA/ATAPI controller(ATA133)
PCI bridge interface(PCI 2.2 Host/
Device, 33MHz/66MHz)
USB2.0 OTG Controller with PHY
Static memory controller
DDR SDRAM controller
DMA controller
10/100Base-T ethernet controller
LCD controller / 656out generator
MMC/SD card controller
AES/DES/3DES cipher controller
5-port UART, TIMER, WDT, RTC, INTC, GPIO, I2C,
SPI/I2S, I2S/AC97, PMU
1.2 V(core), 2.5 V(DDR DRAM I/O) and 3.3 V(I/O)
Package(484-PBGA, 24mmx24mm, 1.0P)
BLOCK DIAGRAM
NVS3211
High Performance H264 DVR System on Chip
DESCRIPTION
NVS3211 is a high performance multi codec(H.264/MPEG4/MJPEG) DVR SoC. It integrates 500MHz ARM9 processor with two 32KB I/D caches, full duplex CIF 240 H.264 codec, USB2.0OTG, PCI and most DVR application-suitable peripherals. Built-in DDR2 controller and NAND/NOR flash controller also play an important role for total BOM cost down. It has fully-hardwired crypto accelerator, SD card controller and high efficient audio DMA Interface module. NVS3211 will be one of the best cost-effective and performance-effective development platforms for various DVR applications.
FEATURES
ARM9 RISC CPU
- up to 533MHz , 32KB I/D-cache, MMU
Video interface
- 2-Ch of BT.656 video inputs
- 2-Ch of BT.656 video outputs
- Maximum input capture resolution up to 1920×1080
- OSD(programmable 12×16 fonts up to 256 characters)
- 656_Out generator with VBI insertion/extraction
H.264 codec
- MPEG4 AVC/JVT/H.264(ISO/IEC 14496-10) baseline profile
- Full duplex encode/decode D1 max 60/60 fps
- CBR and VBR rate control
- Resolution up to 1920×1080 stepped in 16
MPEG4 codec
- MPEG4(ISO/IEC 14496-2) simple profile
- Full duplex encode/decode D1 max 30/30 fps
MJPEG codec
- MJPEG(ISO/IEC 10918-1) baseline standard
- Full duplex encode/decode D1 max 30/30 fps
PCI bridge interface
- Compliant with PCI 3.0 specification(host/target mode)
- 32bit/33MHz, 32bit/66MHz
USB2.0 OTG controller
- Supports UTMI+ level 3 compliant transceiver
- PHY included(LS, FS, HS, HUB function)
DDR2 controller
- 16/32bit DDR II-533 SDRAM interface
NAND/NOR flash controller
- NAND/NOR booting
- NAND flash capacity up to 2GB×4ea
Static memory controller(host port interface)
10/100Base-T Ethernet MAC controller(RMII)
DMA controller
MMC/SD Card controller(SDIO)
Crypto algorithm
- Ciper(AES), hash & HMAC(SHA-1)
Audio DMA
TIMER, WDT, INTC, GPIO, I2C, I2S/SSP, UART, PMU
1.2V(core), 1.8V(DDR2 I/O) and 3.3V(I/O)
Package(484-PBGA, 23 mm×23 mm, 1.0p)
BLOCK DIAGRAM
